Integrated circuitry frequently utilizes CMOS (complementary metal-oxide-semiconductor) for providing operational control relative to other components. For instance, CMOS may be provided adjacent a memory array and utilized for controlling read/write operations associated with the memory array.
CMOS comprises PMOS (p-type metal oxide semiconductor) transistors and NMOS (n-type metal oxide semiconductor) transistors.
A continuing goal of integrated circuit design is to increase the level of integration, and a related goal is to reduce the size of integrated circuit components. In some applications, an integrated device tier (for instance, a memory array) may be provided over CMOS, and electrically coupled with the CMOS. Substantial efforts are made to improve the integration density of the integrated device tier, resulting in substantial reduction in the size of individual components associated with the integrated device tier; and possibly also resulting in a substantial reduction in the overall footprint of the integrated device tier. However, the overall footprint of the integrated device tier and associated CMOS may not be appreciably reduced by increasing the level of integration within the integrated device tier alone. Instead, it would be desirable to also increase the level of integration within the CMOS.
In many applications, fabrication of CMOS utilizes high-temperature processing which would problematically affect an integrated device tier associated with the CMOS. Accordingly, the CMOS is formed before the integrated device tier. Such fabrication sequence limits options available as to the overall placement of the CMOS. It would be desirable to develop new methods for CMOS fabrication which alleviate the requirement for fabricating the CMOS prior to fabricating associated integrated device tiers.